This patent application is based upon and claims the benefit of the earlier filing date of Japanese Patent Application No. 2001-298533 filed Sep. 27, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor chip having a functional block positioned in an SOI (silicon-on-insulator) region and another functional block positioned in a bulk region in a single chip and a method for fabricating such a semiconductor chip.
2. Description of Related Art
DRAM chips having a 1T1C (1-transistor-1-capacitor) memory cell structure have been widely used as an inexpensive and large-capacity memory suitable for high-density integrated circuits. In recent years, demand has been increasing for a system LSI, in which a DRAM and a logic core are integrated in a single chip in order to improve system performance.
On the other hand, SOI devices, such as a SOIMOSFET, using an SOI substrate in place of a conventional silicon bulk substrate has been attracting a great deal of attention. In SOI devices, transistors are formed in the silicon layer positioned on the buried oxide (referred to as xe2x80x9cSOI layerxe2x80x9d) in an SOI substrate. Such SOI devices have already been mass-produced for use in high-performance logic circuits. Along with this trend, in order to further bring out the advantages of a high-performance logic circuit consisting of SOI devices (hereinafter referred to as an xe2x80x9cSOI logicxe2x80x9d), development of a system LSI or a system-on-chip which carries a memory (e.g., a DRAM) together with an SOI logic on a single chip has become an urgent necessity.
However, it is difficult to form a DRAM in an SOI substrate, employing the same structure with the high-performance logic devices (e.g., SOIMOSFETs), for several reasons.
First, leakage current or fluctuation of the threshold voltage will occur during operation because electric potential of the substrate (i.e., the body region) of the SOIMOSFET is floating. If such an SOIMOSFET is used as a path-transistor, leakage current (e.g., a parasitic MOSFET current or a parasitic bipolar-current) occurs depending on the operational conditions of the source/drain voltage, even if the gate voltage is in the OFF condition. For this reason, from a viewpoint of retention, the SOIMOSFET structure is unsuitable for DRAM cell transistors having a strict leakage-current spec.
Second, the threshold voltage varies in accordance with changes in the operational conditions, including operation hysteresis, due to the floating body effect. Accordingly, if the sense amplifier of the DRAM is comprised of SOIMOSFETs, variation in the threshold voltage between the pair transistors is amplified, and the sense margin deteriorates.
To solve the problem of the floating body effect, a technique for fixing the body potential by providing a contact to the additional device region extracted from the body of the conventional MOSFET pattern was proposed. However, this method increases the occupied area of both the memory cell and the sense amplifier greatly, and spoils the high integration feature, which is the main characteristic of a DRAM.
Then it is proposed to form a bulk substrate region as a portion of an SOI substrate, and to form circuits, such as DRAMs, which are incompatible with the floating body effect, in the bulk substrate region. In fact, various methods for fabricating a substrate having both a bulk structure and an SOI structure (referred to as an xe2x80x9cSOI/bulk substratexe2x80x9d) have been proposed.
A first approach is a SIMOX (separation by implanted oxygen) technique using a mask pattern (Japanese Patent Application Laid-open (Kokai) No 10-303385, and Robert Hannon, et al. 2000 Symposium on VLSI Technology of Technical Papers, p66-67). With this method, oxygen is implanted in predetermined positions in the silicon bulk substrate to produce an SOI structure that coexists with the silicon bulk region.
A second approach is a wafer bonding technique for bonding a silicon substrate onto another silicon substrate with a patterned insulator (Japanese Patent Application Laid-open (Kokai) No. 8-316431).
A third approach is to etch the SOI layer and the buried oxide at a predetermined position of the SOI substrate to partially expose the base substrate, thereby producing a bulk region in the SOI substrate (Japanese Patent Application Laid-open (Kokai) Nos. 7-106434, 11-238860, and 2000-91534).
A fourth approach is to form all epitaxially grown silicon layer on the base substrate in order to eliminate the level difference between the SOI substrate region and the bulk region resulting from the partial etching in the third approach (Japanese Patent Application Laid-open (Kokai) No. 2000-243944). In this method the epitaxial layer is grown until it exceeds the mask layer placed over the SOI substrate region, and then it is planarized using the mask layer as a stopper.
There are problems with these approaches to forming an SOI/bulk substrate.
The first approach deteriorates the crystalline characteristic of the SOI layer due to the implantation of oxygen ions. In addition, volume expansion that occurs when the buried oxide is formed by reaction between silicon and the implanted oxygen in a thermal process causes stress, and crystal defect is produced at the boundary between the SOI substrate region and the bulk region.
The second approach produces an undesirable interface state and a crystal-defect layer, which deteriorate both the crystal characteristic and the electrical characteristic at the bonding surface between the two substrates. Such an interface state and crystal defect are due to contamination and shifting of crystal orientation.
The third approach causes a level difference between the SOI substrate region and the bulk region by an amount corresponding to the thickness of the SOI layer and the buried oxide. This level difference makes it difficult to guarantee the focusing margin in the photolithography process, and to control the height of the buried insulator in the trench when forming isolations.
In the fourth approach, the crystal line characteristic of the epitaxial growth layer may deteriorate near the interface between the bulk region and the SOI substrate region. This problem is caused by the fact that crystal grows from both the top face of the base substrate and the sidewall of the SOI layer during the formation of the bulk growth layer. The crystal characteristic of the epitaxial layer having grown from the etched side face of the SOI substrate is inherently bad. In addition, the crystal orientations of the epitaxial layers having grown from the top surface of the base substrate and from the sidewalls of the SOI layer are mismatched with each other at the interface between them further deteriorating the crystal characteristic.
Then, it is conceived to cover the exposed sidewall of the SOI layer with a protection film, such as silicon nitride film, before forming the epitaxial growth layer in order to solve the above-described problem.
However, if a sidewall protection film (e.g., Si3N4) exists at the boundary between the epitaxially grown bulk region and the SOI substrate region, a relatively large stress is produced in both the epitaxial growth layer and the SOI layer over several micrometers near the boundary, depending on the process conditions. Such stress may cause change in the mobility of the carriers and crystal defect. If a transistor is positioned in an area having crystal defect, the device characteristic becomes inferior.
Furthermore, because the epitaxial growth layer is polished using the mask layer as a stopper, the final level of the epitaxial growth layer close to the boundary in the bulk region becomes higher than the SOI layer of the SOI substrate region equivalent to the thickness of the mask layer. To avoid the surface unevenness, a troublesome after-treatment, for example, re-polishing the epitaxial growth layer after thinning the mask layer, must be carried out. If the epitaxial growth layer is set broad in order to form a DRAM macro in it, dishing, which is a phenomenon where a center portion of the layer sinks, occurs. The unevenness of the top surface remains as a step or a level difference in the subsequent processes, and adversely affects the manufacturing process.
Therefore, a novel and improved approach to solving these problems in the conventional methods is desired.
In one aspect of the invention, a semiconductor chip comprises a base substrate, a bulk device region located on a part of the base substrate and having a bulk growth layer, an SOI device region located on the other part of the base substrate and having a buried insulator and a silicon layer located on the buried insulator, and a boundary layer located between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is fabricated, and the SOI device region has a second device-fabrication surface in which an SOI device is fabricated. The first and second device-fabrication surfaces are positioned at substantially the same level.
In another aspect of the invention, a method for fabricating a semiconductor chip comprises (a) preparing an SOI substrate consisting of a base substrate, a buried insulator on the base substrate, and a silicon layer an the buried insulator, (b) removing a portion of the silicon layer and the buried insulator at a predetermined region of the SOI substrate, (c) forming a sidewall protection film covering the side face of the silicon layer exposed by the removal (d) exposing the base substrate at said predetermined region, and forming a bulk growth layer on the base substrate so as to be in alignment with the top face of the silicon layer, (e) forming isolations in the bulk growth layer and the SOI substrate, the isolations having the same depth, and (f) forming devices in the bulk growth layer and the SOI substrate.
In still another aspect of the invention, a method for fabricating a semiconductor chip comprises (a) preparing an SOI substrate consisting of a base substrate, a buried insulator on the base substrate, and a silicon layer on the buried insulator, (b) removing a portion of the silicon layer at a first position on the SOI substrate and forming a first isolation in the removed portion, (c) exposing the base substrate at a second position, while keeping a side face of the silicon layer covered with the first isolation, (d) forming a bulk growth layer from the exposed base substrate so as to be in alignment with the top face of the silicon layer, (e) forming a second isolation in the bulk growth layer, the second isolating being deeper than the first isolation, and (f) forming devices in the bulk growth layer and the SOI substrate
In yet another aspect of the invention, a method for fabricating a semiconductor chip comprises (a) preparing an SOI substrate consisting of a base substrate, a buried insulator on the base substrate, and a silicon layer on the buried insulator, (b) removing a portion of the silicon layer and the buried insulator at a predetermined region on the SOI substrate to expose the base substrate, (c) forming a first part of a trench capacitor having a first width in the exposed base substrate, (d) forming a bulk growth layer from the base substrate so as to be in alignment with the top face of the silicon layer, and (e) forming a second part of the trench capacitor having a second width in the bulk growth layer, the second width being smaller than the first width.
In yet another aspect of the invention, a method for fabricating a semiconductor chip comprises (a) preparing an SOI substrate consisting of a base substrate, a buried insulator on the base substrate, and a silicon layer on the buried insulator, (b) removing a portion of the silicon layer and the buried insulator at a predetermined region on the SOI substrate to expose the base substrate, (c) forming a bulk growth layer from the exposed base substrate so as to be in alignment with the top face of the silicon layer, (d) forming a dummy pattern layer in the bulk growth layer near the boundary between the bulk growth layer and the SOI substrate, the dummy pattern layer being deeper than the buried insulator of the SOI substrate, and (e) forming devices in the bulk growth layer and the SOI substrate.